Transient power control

ABSTRACT

Automatic transient control circuitry may be used to alleviate issues relating to large changes in power demands by a load in an integrated circuit. The transient control circuitry may inject current to or retract current from a load, for example charging or discharging a bypass capacitor associated with the load, when circuitry of the load is commanded to an operational state from a standby state or vice-versa, respectively.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the filing date of (a) U.S.Provisional Patent Application No. 62/012,909, filed on Jun. 16, 2014,(b) U.S. Provisional Patent Application No. 62/013,460, filed on Jun.17, 2014, and (c) U.S. Provisional Patent Application No. 62/086,027,filed on Dec. 1, 2014, the disclosures of which are incorporated byreference herein.

BACKGROUND OF THE INVENTION

The present invention relates generally to power regulation forintegrated circuits, and more particularly to control of transients inpower provided to integrated circuits.

Integrated circuits generally require provision of power withinparticular parameters during operation. The provision of such power mayface many complexities. For example, semiconductor chips including theintegrated circuits may have different portions that require power atthe same or different times, different portions may require power withindifferent parameters, and some portions may utilize different amounts ofpower at different times.

Further complicating matters, some devices may be powered by batterieshaving relatively small capacities, while the devices themselves, atleast at various times, may require large amounts of power. In suchdevices it may be beneficial to provide power only when needed, forexample in order to lengthen effective battery life between charging.Unfortunately, the devices may quickly transition between a staterequiring very little power to a state requiring large amounts of power.In such circumstances, a sudden change in magnitude of a signal on aline or wire through which power is provided may result in transienteffects that cause the provision of power outside the parametersrequired for, or desired for, proper operation of an integrated circuitor device.

BRIEF SUMMARY OF THE INVENTION

Some embodiments in accordance with aspects of the invention provide aDC-DC switching converter that includes a transient control circuit. Insome embodiments in accordance with aspects the transient controlcircuit is an active circuit.

In some embodiments the transient control circuit allows for provisionof power to a load in a ramped manner during a period in which power isto be increased, or reduction in power to the load in a ramped mannerduring a period in which power is to be decreased to the load. In someembodiments the period is a single period, or less than a single period,of the switching converter.

In some embodiments the provision of power to the load in a rampedmanner comprises provision of power to the load in a step-wise manner.In some embodiments provision of power to the load in a step-wise mannercomprises provision of power at a plurality of substantially discretedifferent levels. In some embodiments provision of power at a particularlevel is determined based on one or more comparisons of a signalprovided to the load with pre-defined levels. In some embodiments thesignal is a voltage signal. In some embodiments the period is at astart-up period of provision of power to the load. In some embodimentsthe period is a period in which power to a load is to be increased by apredetermined amount greater than power currently provided to the load.In some embodiments the predetermined amount is based on an amount ofpower currently provided to the load. In some embodiments power isprovided to the transient control circuit, and hence the load, from abattery, or from a system-on-chip power signal. In some embodiments,during the start-up period current is provided through a plurality ofpaths, each coupled either to the load or to ground, with each pathselectively coupled to the load based on comparisons of a signalprovided to the load with pre-defined levels.

In some embodiments the reduction of power to the load in a rampedmanner comprises reducing of power to the load in a step-wise manner. Insome embodiments reduction of power to the load in a step-wise mannercomprises reduction of power at a plurality of substantially discretedifferent levels. In some embodiments reduction of power at a particularlevel is determined based on one or more comparisons of a signalprovided to the load with pre-defined levels. In some embodiments thesignal is a voltage signal. In some embodiments the period is at ashutdown period of provision of power to the load. In some embodimentsthe period is a period in which power to the load is to be decreased bya predetermined amount less than power currently provided to the load.In some embodiments the predetermined amount is based on an amount ofpower currently provided to the load. In some embodiments, during theshutdown period current is pulled through a plurality of paths, eachcoupling the load and to ground, with each path selectively coupled theload to ground based on comparisons of a signal provided to the loadwith pre-defined levels.

In some embodiments voltage across a capacitor is regulated by a DC-DCconverter and several power domains are connected to the capacitor, forexample in a star connection. Each power domain may have a small bypasscapacitor, for example an integrated decoupling capacitor, adjacent tothe power domain on the same silicon. In various embodiments the bypasscapacitor may be a metal-insulator-metal (MIM) capacitor, ametal-oxide-metal (MOM) capacitor, or integrated capacitor otherwiseformed. The power routing between the capacitor being regulated and thepower domain capacitors, which might include package pins, may haveenough parasitic inductance to cause oscillations when the power isincreased or decreased significantly within several clocks of the SoC,which is typically 1 or 2 GHZ (1 nanosecond or 500 picoseconds). In someembodiments passive supply of current from the regulated capacitor tothe capacitors of power domains are aided with an active control circuitthat sources or sinks current in a step-wise manner, for example causingprovision of power at a plurality of substantially discrete differentlevels. In some embodiments provision of power at a particular level isdetermined based on one or more comparisons of a signal provided to theload with pre-defined levels. In some embodiments the signal is avoltage signal.

In some embodiments the active control circuit sources current duringthe startup period, keeping the voltage difference between the capacitorof the power domain and the regulated capacitor relatively constant(typically within −50 mV), which results in linear increase of thecurrent across the parasitic inductor with minimum passive oscillations.

In some embodiments the power being delivered to the power domain isdesired to be shut down, and the active control circuit sinks currentduring a shutdown operation. This is preferably accomplished in a mannerto keep the voltage difference between the capacitor of the power domainand the regulated capacitor relatively constant (typically within +50mV), which results in linear decrease of the current across theparasitic inductor with minimum passive oscillations

In some embodiments the transient control circuit instead or in additionincludes a gate coupled across nodes of an inductor forming part of theDC-DC switching converter. In some embodiments the gate allows forpassage of current. In some embodiments the gate allows for passage ofcurrent during a start-up period of provision of power to a load.

In some embodiments the DC-DC switching converter includes an inductorand a capacitor, with provision of power from a node between theinductor and the capacitor. In some such embodiments the transientcontrol circuit includes a gate coupled across nodes of the inductor,and ramping start-up circuitry to provide current to a load in a rampedmanner during a start-up period for the load.

Some embodiments in accordance with aspects of the invention includepower supply circuitry for a system-on-chip, with the power supplycircuitry including a plurality of DC-DC switching converters eachincluding a capacitance and an inductance, and transient controlcircuitry for at least a plurality of the DC-DC switching converters.

Some embodiments in accordance with aspects of the invention provide amethod useful in control of power to a power domain of an integratedcircuit, comprising: determining if circuitry of a power domain is totransition from a standby low power state to an operational state; ifthe circuitry is to transition from the standby low power state to theoperational state: providing power from a first power source to thecircuitry of the power domain using a DC-DC switching converter, andproviding current from a second power source to the circuitry of thepower domain on at least one selectable path.

Some embodiments in accordance with aspects of the invention provide amethod useful in control of power to a power domain of an integratedcircuit, comprising: determining if circuitry of a power domain is totransition from an operational state to a standby low power state; ifthe circuitry is to transition from the operation state to the standbylow power state: drawing current from a node used to provide power tothe circuitry of the power domain on at least one selectable path.

Some embodiments in accordance with aspects of the invention providecircuitry useful in controlling transients in a power distributionsystem, comprising: a DC-DC switching converter coupled to a node forapplying voltage to a power domain load; and a digitally controlledcurrent source coupled to the node for applying voltage to the powerdomain load, in parallel with the DC-DC switching converter.

Some embodiments in accordance with aspects of the invention provide asystem with a power transient control circuitry comprising: a firstswitch and a second switch coupled in series between a higher powersource and lower power source; an inductor having one end coupledbetween the first and second switch and another end coupled to acapacitor and a power load in parallel; and a first plurality of pathsselectively couplable between the higher power source and the powerload, each of the first plurality of paths having a switch forselectively coupling the path between the higher power source and thepower load.

These and other aspects of the invention are more fully comprehendedupon review of this disclosure.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a semi-schematic, semi-block diagram of a system includingpower transient control circuitry in accordance with aspects of theinvention.

FIG. 2 is a semi-schematic, semi-block diagram showing portions ofembodiments of power transient circuits in accordance with aspects ofthe invention.

FIG. 3A is a semi-schematic, semi-block diagram showing portions of afurther embodiment of power transient circuits in accordance withaspects of the invention.

FIG. 3B is a further semi-schematic, semi-block diagram showing portionsof a further embodiment of power transient circuits in accordance withaspects of the invention.

FIG. 4 is a semi-schematic, semi-block diagram showing power supply andtransient control for a multiple power domain system in accordance withaspects of the invention.

FIG. 5 is a flow diagram of a process useful in providing for transientcontrol for supply of power in or to an integrated circuit, inaccordance with aspects of the invention.

FIG. 6 is a semi-schematic, semi-block diagram showing portions offurther power transient control circuitry in accordance with aspects ofthe invention.

FIG. 7 is a flow diagram of a further process useful in providing fortransient control for supply of power in or to an integrated circuit, inaccordance with aspects of the invention.

DETAILED DESCRIPTION

FIG. 1 is a semi-schematic, semi-block diagram including circuitry inaccordance with aspects of the invention. As shown in FIG. 1, a powersource 111 provides power to a DC-DC switching converter. The DC-DCswitching converter includes a push-pull switch including a high sideswitch 113 and a low side switch 115 in series between the power sourceand a ground. A first node of an inductor 119 is coupled between thehigh side switch and the low side switch, with a second node of theinductor coupled by way of a capacitor 121 to ground.

The high side switch and the low side switch are generally controlled ina synchronous manner by control circuitry 117. The control circuitrygenerally controls the switches based on various feedback signals, forexample a signal indicative of inductor current, a signal indicative ofvoltage at a node between the capacitor and the inductor, and variousother signals. In general, the control circuitry controls the switchesto obtain a desired voltage at the node between the inductor and thecapacitor, generally the capacitor voltage. The capacitor voltage isgenerally used to provide power to a load, which may be multiple loads,in a power domain 123.

In some embodiments some or all of the power source, inductor, andcapacitor are located off of a semiconductor die with the semiconductordie including the load, with the other components on the semiconductordie.

An active transient control block 125 includes circuitry for controllingtransients in power supplied to the power domain. The active transientcontrol block 125 allows for passage of power from the power source, orsome other power source in some embodiments, to the power domain. Invarious embodiments an on-chip capacitor, or multiple on-chipcapacitors, may be provided in parallel in parallel to the power domainor load. In some embodiments the active transient control block providescurrent to an on-chip capacitor in parallel to the load. In someembodiments the active transient control block may provide current tocapacitors, for example in-package but not on-chip capacitors, in apower delivery network between the generally off-chip and possibleoff-package capacitor of the DC-DC converter. In some embodiments thismay be selectively accomplished through use of a switch, which may beselectively enabled by the control 117 or otherwise, coupling the activetransient control block of the in-package capacitors. In addition, invarious embodiments the active transient control block allows forpassage of power from the capacitor to the power domain. In addition, insome embodiments the active transient control block is coupled to bothnodes of the inductor. In some embodiments the active transient controlblock limits the current delivered from the capacitor to the powerdomain by delivering additional current during abrupt increases in powerdemand by the elements in the power domain. In some embodiments theactive transient control block limits the current between the capacitorand the power domain by sinking current during abrupt decreases in powerdemand by the elements in the power domain.

As illustrated in FIG. 1, the active transient control block is coupledto a node between the high side switch and the inductor, and couplesthat node to the power domain. The active transient control blocktherefore allows coupling of the power domain to the power source,through for example the high side switch. In some embodiments the activetransient control block may be coupled to the power source, or someother power source, through some other coupling.

In some embodiments, and as illustrated in FIG. 1, the active transientcontrol block is also coupled to the second node of the inductor and tothe power domain, with the active transient control block coupling thepower domain to the second node of the inductor, and hence thecapacitor.

In some embodiments the active transient control block includescircuitry for providing power to the power domain from the power source,preferably in a controlled ramping manner, during predefined operationalconditions. For example, in some embodiments, when the power domainrequires a large increase in supplied power, the active transientcontrol block may allow, over a period of time, increasing amounts ofpower to be supplied from the power source to the power domain.

In some embodiments this may be accomplished by providing a plurality ofparallel signal paths from the power source to the power domain, each ofthe paths being able to pass discrete amounts of power to the powerdomain. Differing numbers of paths, or different paths allowing forpassage of differing amounts of power to the power domain, may beactivated at different times during the period of time. The period oftime may be relatively short, for example, limited to nominally a cycleof a switching power duty cycle. In some embodiments selection of whichpaths to activate, and in some embodiments when to activate the paths,may be made based on magnitude of voltage at an input to the powerdomain. In some embodiments the magnitude of the voltage may bedetermined by use of comparators, which preferably are relatively fastacting comparators. In some embodiments each of the paths may include anoutput branch coupled to the power domain and another output branchcoupled to a ground. During times when any of the paths are to beactivated, or may be activated, power may be passed through all of thepaths, selectively either to the power domain or to the ground, or toboth. Such a configuration, which may be implemented for example usingcurrent mirrors, may allow for decreased activation time when power isdesired to be passed through a particular path to the power domain,and/or may provide possible reduction of voltage drops across parasiticinductances in a supply path from the power source to the activetransient control block.

Such operation may considered a fast start-up mode, and may be active ortriggered when there is a large negative internal node voltage error,for example when voltage supplied to the power domain is lower than apredefined magnitude. Such an occurrence may occur due to fast start-upwhich causes the voltage to fall below a threshold during the first timewhen the high side switch is on following a standby mode for the powerdomain. In some embodiments activation of the fast start-up mode occursonly upon an exit from standby mode for the power domain, or atransition from a standby mode to an on or start mode, or either or bothand a large negative internal node voltage error. In various embodimentsthe fast start-up mode may end when either or both the low voltage errorcondition is no longer true or after a first cycle of DC-DC converteroperation, which may be for example 18 nsec for a switching converterusing an inductor of 10 nH.

In some embodiments the active transient control block is in standbymode when the DC-DC converter is in STANDBY mode. The active transientcontrol circuitry may be powered up when the DC-DC high side switchturns on when voltage across the external capacitor is below the presetthreshold (typically −1%) and provides start-up transient control ifenabled by a second threshold. Active transient startup control may beenabled when the internal node voltage falls below a second presetthreshold (typically −2%), with the active transient control block thendelivering additional current. In some embodiments this can beimplemented as digitally controlled current source (for example 5 to 10current mirrors that are enabled/disabled depending on a level of theinternal node voltage). The power may only be provided, and the activetransient control block circuitry for providing the current may only beactive, during a first cycle of the switching converter when the highside switch is on. The duration and magnitude of the current may dependon a ramp rate and final value of the load current, which may not beknown but the number of current mirrors enabled based on the internalnode voltage error can be used to estimate the load current. This initself provides useful information regarding the load current without aneed for additional monitoring other than the voltage. The circuitdeactivates itself and the deactivation signal can be used to start thenormal operation of the DC-DC controller which remains in power switchON mode until active transient start-up is deactivated. In someembodiments the number of current mirrors activated can also be used todetermine whether the DC-DC converter should immediately follow in PWMmode or provide single pulse and return to standby.

In addition, in some embodiments, the active transient control blockalso isolates the power domain from the capacitor during fast start-upmode. In such instances, in some embodiments the active transientcontrol block may also couple the first node and the second node of theinductor, for example so as to effectively short the two ends of theinductor. In some embodiments the active transient control block maycouple the inductor nodes using a one-way switch.

In some embodiments the active transient control block also includescircuitry for implementing a forced standby mode. In some embodimentsthe active transient control circuitry may couple the two inductornodes, effectively shorting them, in some embodiments using a one wayswitch. Forced standby mode may be active when there is a large positivevoltage error on the capacitor; for example due to large inductorcurrent that could not be handled by the DC-DC control (or somehow wasnot handled). In some embodiments forced standby conditions arecontinuously monitored, and reset when the error condition iseliminated. During forced standby the DC-DC high side switch and lowside switch control signals may be determined, but the control signalsdisabled, for example based on a control signal from the activetransient control block. In some embodiments the forced standby modeinductor current is monitored, with the mode ending when the current isbelow a preset threshold. The capacitor voltage may also be monitored,and if the capacitor voltage error falls below threshold (typically +1%)the forced standby mode additionally or alternatively ends.

Accordingly, in some embodiments during forced standby both the highside and low side switches are off. In some embodiments, unlike faststart-up mode, the forced standby functionality is not limited to aspecific period and would be engaged every time the voltage error acrossthe external capacitor is above 2% threshold. In some embodiments forcedstandby mode may be exited if either (or both, in some embodiments) thevoltage error across the external capacitor is below the presetthreshold or the voltage across the connections to the inductor nodesfalls below a certain threshold as this is an indication of smallinductor current. When reset ATC returns to the same mode as DC-DCcontroller (Active or Standby).

FIG. 2 is a semi-schematic, semi-block diagram showing portions of anembodiment of an active transient control block, which in someembodiments may be part of the active transient control block of FIG. 1.For clarity, FIG. 2 also shows a high side switch 213, low side switch215, inductor 216, and capacitor 217 of a DC-DC converter, and a load219. Similar to the discussion with respect to FIG. 1, the high sideswitch and the low side switch are coupled in series between a powersource and a ground, with the power source coupled to the high sideswitch and the ground coupled to the low side switch. A first node ofthe inductor is coupled to a node between the high side switch and thelow side switch, and a second node of the inductor is coupled to aground by way of the capacitor. The DC-DC converter supplies power froma node between the inductor and the capacitor. Depending on a type ofconverter used, and implementation details, one of skill in the art mayrecognize that other configurations may instead be used.

An isolation switch 221 separates the capacitor and the load, with theisolation switch serving to isolate the load from the DC-DC converterbased on an isolation control signal ISOCTL. ISOCTL may be set by acontroller, for example an active transient control controller, a DC-DCconverter control, or a system-on-chip (SOC) signal, depending onimplementation.

The active transient control block includes fast start up circuitry 223.In the embodiment of FIG. 2, the fast startup circuitry provides aplurality of paths 225 a-d between an SOC power supply Vcc and the load.In some embodiments, however, the plurality of paths 225 a-d providepaths between a line coupled to a node, the node between the high sideswitch and the low side switch (which may be termed an inductorswitching node), and the load. In such embodiments, in most cases, aswitch will couple the paths to the node, and in some embodiments theswitch may be part of a bypass switch, discussed later with respect togate 231 of FIG. 2. In such instances the bypass switch may includemultiple branches. With respect to the paths, each of the paths includesa switch S1-S4 for activating the path. In addition, in the embodimentof FIG. 2, an enable switch 227 is between the SOC power supply and thepaths, such that none of the paths receives power unless the enableswitch is turned on. In addition to or instead of any other control ofthe enable switch discussed herein, in some embodiments the enableswitch is maintained in an off state if a digital voltage frequencyscaling governor or similar circuitry is operating the power domain at alow frequency, or a frequency below a predetermined frequency.Similarly, in some such embodiments, other or all of the ATC circuitryis maintained in an unpowered state in such a situation.

The active transient control block also includes one or more comparators229 for comparing voltage provided to the load with predeterminedvalues, which in some embodiments are programmable, for example by wayof register settings or otherwise. In some embodiments the comparatorsmay instead compare voltage of an output capacitor of the DC-DCconverter, and in some embodiments the comparators may be external tothe active transient control block. In some embodiments thepredetermined values are representative of voltages within predefinedamounts of a desired output voltage. In some embodiments the desiredoutput voltage may be determined or provided by a controller, forexample the controller 117 of FIG. 1. In some embodiments thecomparators determine a magnitude of a negative voltage error in voltageapplied to the load.

In operation, in some embodiments, upon entry into a fast startup mode,the enable switch is turned on, as are, on a sequential basis in someembodiments, a plurality of the paths, through activation of theiractivation switches. In some embodiments, the plurality of paths areactivated based on a magnitude of a negative voltage error in voltageapplied to the load, with increased number of paths activated withincreasing negative magnitude of error. In some embodiments theplurality of paths are activated based on the magnitude of the negativevoltage error, with paths activated to provide desired current to theload. In some embodiments the isolation switch is also set to isolatethe load from the DC-DC converter during fast startup mode. In manyembodiments, however, during fast start-up the isolation switch is setto not isolate the load from the capacitor so as to provide current fromthe capacitor while inductor current is ramping up.

Generally, on exit of fast startup mode the enable switch is set low,the path switches are set low, and the isolation switch is set to notisolate the load from the DC-DC converter.

In addition, in some embodiments, and as illustrated in FIG. 2, a gate231 is provided to selectively couple ends of the inductor. The gate 231may be considered to place the DC-DC converter in a bypass mode, and thegate 231 may therefore be considered in some embodiments a bypassswitch. In some embodiments the gate 231 is turned on during faststartup mode, but in most embodiments during fast startup mode typicallygate 231 is turned off, the high side switch is turned on (with the lowside switch turned off) and the current of the inductor is ramping. Inaddition, in some embodiments the gate is turned on in fast shutdownmode, and/or in some embodiments the gate is turned on when anindication of inductor current is significantly greater, or greater thana predetermined amount or factor, than a desired load current.

One version of the fast startup circuitry is implemented with six paths,a current mirror for each path. Each path may be activated using presetthresholds as summarized in the table below. In some embodiments thefast startup circuitry is only activated during a first high side switchon pulse and there is an automatic deactivation when the voltage appliedto the load returns to a regulation range (e.g. below smallestthreshold).

Number of Current IntVO activation Mirrors ENABLED threshold 0 +/−1%   1 −1% error 2 −2% error 3 −3% error 4 −4% error 5 −5% error 6 −6% error

In various embodiments outputs of the comparators 229 are used todetermine the number of current mirrors enabled. In various embodimentsoutputs of the comparators are used to determine an index to a look-uptable (LUT), with the LUT indicating a number of current mirrors toenable. In some embodiments a plurality of LUTs may be used, anddifferent LUTs may indicate a different number and/or different ones ofthe current mirrors enabled. In some such embodiments use of aparticular LUT may be selected based on a rate of change of poweravailable to the load with respect to desired power available to theload, for example as indicated by rate of change of negative voltageerrors. For example, different LUTs may be used depending on whether thenegative voltage error is rapidly increasing, rapidly decreasing, orneither rapidly increasing or rapidly decreasing.

FIG. 6 is a semi-schematic of a further embodiment of portions of anactive transient control block in accordance with aspects of theinvention, and in some embodiments may serve as the active transientcontrol block of the embodiment of FIG. 1. As with FIG. 2, for clarityFIG. 6 also shows a high side switch 613, low side switch 615, inductor616, and capacitor 617 of a DC-DC converter, and a load 619. The activetransient control block also includes one or more comparators 629 forcomparing voltage provided to the load with predetermined values, whichin some embodiments are programmable, for example by way of registersettings or otherwise.

Similar to the discussion with respect to FIG. 1, the high side switchand the low side switch are coupled in series between a power source anda ground, with the power source coupled to the high side switch and theground coupled to the low side switch. A first node of the inductor iscoupled to a node between the high side switch and the low side switch,and a second node of the inductor is coupled to a ground by way of thecapacitor. The DC-DC converter supplies power from a node between theinductor and the capacitor. Also as in FIG. 2, in FIG. 3 an isolationswitch 621 separates the capacitor and the load, with the isolationswitch serving to isolate the load from the DC-DC converter based on anisolation control signal ISOCTL. ISOCTL may be set by a controller, forexample an active transient control controller, a DC-DC convertercontrol, or a system-on-chip (SOC) signal, depending on implementation.

The active transient control block includes fast startup/fast shutdowncircuitry 623. In the embodiment of FIG. 6, the fast startup/shutdowncircuitry provides a first plurality of paths 625 a-d between an SOCpower supply Vcc and the load, and a second plurality of paths 626 a-dbetween a node, between the first plurality of paths and the load, and aground. Each of the first paths includes a switch S1-S4 for activatingthe path, and each of the second paths include a switch SN1-SN4 foractivating the path. In addition, in the embodiment of FIG. 6, an enableswitch 627 is between the SOC power supply and the first paths, suchthat none of the first paths receives power unless the enable switch isturned on. As discussed with respect to the enable switch 227 of FIG. 2,if a DVFS governor or similar circuitry is operating the power domainload at a low power, low frequency condition, the enable switch may bekept in an off state. In addition, in some embodiments a further enableswitch (not shown) may be provided between the second paths and ground,such that none of the second paths sink power unless the further enableswitch is turned on.

The fast startup/shutdown circuitry may be operated as discussed withrespect to FIG. 2 in order to provide a fast startup mode. In addition,in some embodiments the second paths may used to provide a fast shutdownmode. For example, in some embodiments selected ones, or all, of thesecond paths are activated when the comparators indicate a largepositive voltage error in voltage applied to the load, with for examplepaths activated so as to sink increasing amounts of current forincreasing large positive voltage errors. Such a circumstance may occur,for example, when the load is commanded to be off, for example based ona command generated elsewhere on a SOC. In some embodiments, during fastshutdown the isolation switch may be maintained in an on state for aswitching cycle period of the converter.

FIG. 3A is a semi-schematic of a further embodiment of portions of anactive transient control block in accordance with aspects of theinvention, and in some embodiments may serve, or portions may serve, asthe active transient control block of the embodiment of FIG. 1.

In the embodiment of FIG. 3A, a power domain isolation switch links faststartup circuitry 313 to a DC-DC converter (not shown in FIG. 3A). Thefast startup circuitry couples a power source 315, VDD_SOC in thisexample, to a load (not shown in FIG. 3A). The fast startup circuitryincludes an enable switch 317 coupling the power source to a pluralityof paths 1-N. Each of the paths may be implemented as discussed herein.In operation, during a fast startup mode, a first path is activatedusing a control switch 317 a at a first threshold of negative error involtage applied to the load, a second path is activated using a controlswitch 317 b at a second threshold of negative error in voltage appliedto the load, . . . , an xth path is activated using a control switch 317c at an xth threshold of negative error in voltage applied to the load,. . . , and an Nth path is activated using a control switch 317 d at anNth threshold of negative error in voltage applied to the load.

One version of the fast shutdown circuitry is implemented with sixpaths, a current mirror for each path. Each path may be activated usingpreset thresholds as summarized in the table below. In some embodimentsthe fast shutdown circuitry is only activated when SOC signal to isolatepower domain is received and there is an automatic deactivation when thevoltage applied to the load returns to a regulation range (e.g. belowsmallest threshold) or after a fixed period typically the same as asingle cycle of switching regulator.

Number of Current IntVO activation Mirrors ENABLED threshold 0 +/−1%   1 +1% error 2 +2% error 3 +3% error 4 +4% error 5 +5% error 6 +6% error

FIG. 3B is a semi-schematic of a further embodiment of portions of anactive transient control block in accordance with aspects of theinvention, and in some embodiments may serve, portions may serve, as theactive transient control block of the embodiment of FIG. 1.

In the embodiment of FIG. 3B, an active transient control block 351couples power from VDD to a power domain load 353. The power domain loadis also coupled to power by way of a DC-DC converter, although such isnot shown in FIG. 3B, and the power domain load may be provided powerfrom the DC-DC converter, for example as discussed with respect to FIG.3A.

The active transient control block includes a plurality of paths forproviding power from VDD to the power domain load, with two paths shownin FIG. 3B for illustrative purposes. Each of the paths is gated by aswitch 359 a,b. Operation of each switch is based on an enable signalfor that switch, and on a comparison of one or more reference voltageswith voltage being applied to the power domain load. In some embodimentsthe reference voltages are as discussed with respect to FIG. 3A, forexample. In some embodiments a signal activates a switch for a path,coupling VDD to the power domain load, when the enable signal for thatswitch is active and a reference voltage for that path is less than thevoltage being applied to the power domain. In some embodiments thesignal activating the switch is also held in the activating state for atleast a preset period after activation, for example one clock cycle or apredetermined number of clock cycles.

In some embodiments the switch may operate in a range of activation,with the switch for example being one or more transistors operated intheir linear range during activation. The extent of activation, andtherefore magnitude of current provided by a path, may be based on adifference between the reference voltage for the path and the voltageapplied to the power domain load. In addition, the activation of theswitch may maintained in an active state for at least a predeterminedtime after activation, or for a predetermined period of time after theenable signal for that switch becomes active.

This is somewhat diagrammatically shown in FIG. 3B. In FIG. 3B a controlcircuitry for each path includes an analog comparator 355 a,b and asample and hold circuit 357 a,b. In some embodiments the analogcomparator is formed of a low gain differential amplifier or othercircuitry. The analog comparator for a path compares its referencevoltage with voltage applied to the power domain, and provides a signalindicative of a difference between the two to a sample and hold circuitfor that path. The sample and hold circuit outputs an equivalent signalwhen the enable signal is active, and for a predetermined time periodafter the enable signal become inactive. In some embodiments the outputof the analog comparator is tuned such that output voltage from theanalog comparator will operate the enable switches in their linear rangefor a predetermined range of differences between the reference voltageand the voltage applied to the power domain load.

In some embodiments extent of activation of a switch for a path is basedon a magnitude of a rate of change of a reference voltage for the pathwith respect to the voltage applied to the load, or in some embodimentsvice versa. In some such embodiments a differentiating amplifier, forexample, or a sample and hold differential amplifier may be used incontrol the switch for the path.

FIG. 4 is a semi-schematic, semi-block diagram of a further device inaccordance with aspects of the invention. In FIG. 4, multiple powerdomains are powered using a multiphase switching regulator 411. In FIG.4 the switching regulator operates a first pair of switches 413 a withassociated inductor 415 a at a first phase and a second pair of switches413 b with associated inductor 415 b at a second phase. Each of theinductors is coupled to a common capacitor 417. In various embodimentsmore than two such sets, for example 16 such sets, may be so operated bythe switching regulator. The use of such a multi-phase operation may bebeneficial in maintaining capacitor voltage at a relatively stablevalue. In some embodiments of a multiphase implementation when allphases are in standby; the power domains associated with a first phasethat changes mode from standby to active is considered for fast startupactivation, and in some such embodiments only the first phase is soconsidered. In this case fast startup is only activated during the firsthigh side cycle of this phase, and consecutive phases are not consideredfor fast startup. During the first cycle of the first phase all powerdomains associated with the first phase, with ISO switch ON, canactivate fast startup.

The regulator generally controls provision of power to a plurality ofpower domains. In the embodiment of FIG. 4, power domains 1, 2, N-1, andN are illustrated. Power domains 1 and 2 are coupled to power by way ofactive transient control blocks 419, 421, respectively. The activetransient control blocks 419, 421 are also coupled across respectiveones of the inductors. The active transient control blocks 419, 421 maybe implemented, for example, as discussed with respect to FIGS. 1 and/or2, and may implement both fast startup mode operations and forcedstandby modes. Power domains N-1 and N are coupled to power by way ofactive transient control blocks 423, 425, respectively. Active transientcontrol blocks 423, 425 are not coupled across inductors. Activetransient control blocks 423, 425 may be implemented, for example, asdiscussed with respect to FIG. 1 and/or 3 (including the coupling toVCC_SOC), and implement fast startup mode but do not implement forcedstandby mode.

In some embodiments an SoC would indicate upcoming transients withPOWERUP/POWERDN and ISOLATE control signals. In some embodiments thecontrol signals may be used, instead or additionally to enter which willdetermine fast startup and fast shutdown modes, and to allow forregulator control operation based on the information obtained from thesetransient events. In some embodiments, in all cases, the regulatorcontroller acting independently based on the voltage error on theexternal capacitor (for example +2% to forced standby, −1% to activate)can activate a phase or go to forced standby. If the regulatorcontroller activates a first phase when all phases are in standby, allpower domains with ISO switch ON can activate fast startup regardless ofwhether they have received POWERUP signal.

FIG. 5 is a flow diagram of an example process for determining entry tofast startup mode and forced standby mode. The process of FIG. 5 may beperformed by a controller, for example implemented directly in circuitryor circuitry executing program instructions.

In block 511 the process determines if the converter has started or isin standby mode. If started (not in standby mode) the process continuesto block 513. In block 513 the process determines if voltage applied toa load is less than a predetermined error threshold. If so, the processgoes to block 515, and enters startup mode. Otherwise the processcontinues to block 517. In block 517 the process determines if capacitorvoltage is greater than a predetermined error threshold. If so, theprocess goes to block 519, and enters forced standby mode.

In some embodiments forced standby conditions are continuouslymonitored, and reset when the error condition is eliminated. Duringforced standby the DC-DC high side switch and low side switch controlsignals may be determined, but the control signals disabled, for examplebased on a control signal from the active transient control block. Insome embodiments the forced standby mode inductor current is monitored,with the mode ending when the current is below a preset threshold. Thecapacitor voltage may also be monitored, and if the capacitor voltageerror falls below threshold (typically +1%) the forced standby modeadditionally or alternatively ends.

In some embodiments forced standby conditions are continuously monitoredand can be activated to handle overvoltage on the capacitor connected tomultiple power domains. Each power domain can independently activatefast startup and fast shutdown.

The process thereafter returns.

FIG. 7 is a flow diagram of an example process for determining entry tofast shutdown mode. The process of FIG. 7 may be performed by acontroller, for example implemented directly in circuitry or circuitryexecuting program instructions. In some embodiments fast shutdown modeoccurs when there is an isolation command and a large positive internalvoltage error. In some embodiments, in fast shutdown mode currentmirrors, coupled to a node to which voltage is applied to power a load,are turned on based on the voltage error, to sink current to ground.

In block 711 the process determines if a command to isolate a powerdomain has been received. If so, the process continues to block 713 anddetermines if voltage applied to the power domain is above apredetermined error voltage. If so, the process enters fast shutdownmode in block 715. The fast shutdown mode may operate as discussedherein. If fast shutdown mode is entered, or if the voltage applied tothe power domain is not above the predetermined error voltage, theprocess determines if a predetermined period has ended in block 717. Insome embodiments the predetermined period is one duty cycle of a DC-DCconverter. If the period is over the process continues to block 719 toturn off an isolation switch, isolating the load from power, andthereafter returns. Otherwise the process returns to block 713 toperform another voltage comparison.

Although the invention has been discussed with respect to variousembodiments, it should be recognized that the invention comprises thenovel and non-obvious claims supported by this disclosure.

1.-24. (canceled)
 25. Circuitry useful in controlling transients in apower distribution system, comprising: a DC-DC switching convertercoupled to a node for applying voltage to a power domain load; and afirst plurality of paths between a power source and the node, each ofthe first plurality of paths including at least one transistor forselectively coupling the path between the power source and the node,based on an enable signal and an output of a comparator comparing anindication of voltage at the node and at least one reference voltage.26.-29. (canceled)
 30. The circuitry of claim 25, wherein a magnitude ofcurrent supplied by a particular current path of the first plurality ofpaths is based on a magnitude of the output of the comparator. 31.-32.(canceled)
 33. The circuitry of claim 25, further comprising anisolation switch coupled between the DC-DC switching converter and thenode. 34.-36. (canceled)
 37. The circuitry of claim 25, furthercomprising a second plurality of paths between the node and a lowerpower source, each of the second plurality of paths having a switch forselectively coupling the path between the node and the lower powersource. 38.-40. (canceled)
 41. The circuitry of claim 25, wherein thecomparator is an analog comparator, the analog comparator the providinga difference signal indicative of a difference between the indication ofvoltage at the node and the reference voltage.
 42. The circuitry ofclaim 41, wherein the comparator comprises a differential amplifier. 43.The circuitry of claim 41, further comprising a sample and hold circuit,the sample and hold circuit coupled to the comparator so as to receivethe difference signal and the enable signal, an output of the sample andhold circuit coupled to the at least one transistor.
 44. The circuitryof claim 41, wherein the difference signal operates the at least onetransistor in a linear range of the at least one transistor.
 45. Thecircuitry of claim 25, wherein the reference voltage is different foreach of the first plurality of paths.